VHDL EDGE DETECTION SYNOPSIS

INTRODUCTION

VHDL was developed to provide a standardized and technology independent way to describe formally the behavior and structure of digital electronic systems. It offers the technical means to provide functional, timing, and other specifications for digital electronic systems in a form that will be useful long after the original system is delivered. Technology independence permits the separation of the behavior function (plus timing) from its implementation, which makes incorporating new technologies easier.
The main goal of image processing is to create systems that can scan objects and make judgments on objects at rates many times faster than that of a skilled human observer. Naturally, the first step in building such systems is to identify the imaging functions that allow a computer-based system to behave like a trained human operator. With this achieved the emphasis can then be placed on making that system run faster, and in order to do this you need to find the biggest performance bottleneck in the system and remove it.

WORKING PRINCIPLE

Edges are considered to be most important image attributes that provide
valuable information for human image perception. With the advent of
artificial intelligence systems and forensic science the process of edge
detection has achieved the most sought status. Edge detection is a very
complex process affected by deterioration due to different level of noise.
A number of operators are defined to solve the problem of edge detection
[1–6]. They behave well in one application but poorly in other.

Before an image can be segmented, the objects in that image must be detected and roughly classified as to shape and boundary characteristics (edges).
Edges are significant local changes in the image and are important features for analyzing images. Edge detection is frequently the first step in recovering information from images. Many dge detectors, such as Roberts Operator, Sobel operator, Prewitt Operator, Laplacian Operator, etc., have been developed in the last two decades. Since the Sobel operator is one of the most commonly used edge detectors in image processing systems, we used this operator to illustrate our design methodology.

Consider the arrangement of pixels about the pixel [i, j] shown in Figure 2.7 [5]. The Sobel operator is the magnitude (M) of the gradient computed by

EH , EV , EDL and EDR are the absolute values of EH , EV , EDL , EDR , respectively. E^ is the absolute value in the direction perpendicular to the direction of the maximum absolute value. EH , EV , EDL and EDR are called the differences in intensity along the horizontal, vertical, and left and right diagonal direction, respectively. They can be calculated individually by convoluting the image with four 3 x 3 windows (i.e., the Sobel operators) as shown in Figure

This procedure is also called filtering.The magnitude (M) is then compared to a particular threshold to determine the edge pixels. A pixel is declared to be an edge pixel if and only if M is greater than or equal to the threshold.

Example of Horizontal Filter

Direction Assignment

Figure shows a convolution table containing the pixel located at coordinate [i; j] and its eight neighbors. As shown in Figure 2, the table is moved across the image, pixel by pixel. For a 256£256 pixel image, the convolution table will move through 64516 (254£254) different locations. The algorithm in Figure 4 shows how to move the 3£3 convolution table over a 256£256 image. The lower and upper bounds of the loops for i and j are 1 and 254, rather than 0 and 255, because we cannot calculate the derivative for pixels on the perimeter of the image.

The Sobel edge detection algorithm identifies both the presence of an edge and the direction of the edge (Figure 6). There are eight possible directions: north, northeast, east, southeast, south, southwest, west, and northwest.

For each direction, Figure shows an image sample, a convolution table, and the encoding of the direction. In the image sample, the edge is drawn in white and direction is shown with a black arrow. Notice that the direction is perpindicular to the edge. The trick to remember the edge direction is that the direction points to the brighter side of the edge. The eight directions are grouped into four orientations: NE SW, N S, E W, and NW SE.

For a convolution table, calculating the presence and direction of an edge and is done in three major steps:

1. Calculate the derivative along each of the four orientations. The equations for the derivatives are written in terms of elements of a 3£3 table

Deriv NE SW = (table[0;1]+2£table[0;2]+table[1;2]) ¡ (table[1;0]+2£table[2;0]+table[2;1])
Deriv N S = (table[0;0]+2£table[0;1]+table[0;2]) ¡ (table[2;0]+2£table[2;1]+table[2;2])
Deriv E W = (table[0;2]+2£table[1;2]+table[2;2]) ¡ (table[0;0]+2£table[1;0]+table[2;0])
Deriv NW SE = (table[1;0]+2£table[0;0]+table[0;1]) ¡ (table[2;1]+2£table[2;2]+table[1;2])

2. Find the value and direction of the maximum derivative, and the absolute value of the derivative that is perpindicular to the maximum derivative.
EdgeMax = Maximum of absolute values of four derivatives
DirMax = Direction of EdgeMax
EdgePerp = Absolute value of derivative of direction perpindicular to DirMax

3. Check if the maximum derivative is above the threshold. When comparing the maximum derivative to the threshold, the Sobel algorithm takes into account both the maximum derivative and the derivative in the perpindicular direction.
if EdgeMax + EdgePerp/8 >= 80 then
Edge = true
Dir = DirMax
else
Edge = false
Dir = 000

Row Count of Incoming Pixels

The output signal o row shall show the row number (between 0 and 255) for the most recent pixel that was received from the PC. The signal o row shall be initialized to 0. When the last pixel of the image is sent to the FPGA, o row shall be 255. The seven-segment controller in top sobel architecture displays the value of o row on the seven segment display of the FPGA board.

Memory

256£256 bytes (=65536 pixels) will be sent to the Sobel circuit byte by byte either by a testbench (for functional and timing simulation) or by PC to the FPGA (for real test on FPGA board) through the serial port. As illustrated below, you can do Sobel edge detection by storing only a few rows of the image at a time.
To begin the edge detection operations on a 3£3 convolution table, you can start the operations as soon as the element at 3rd row and 3rd column is ready. Starting from this point, you can calculate the operations for every new incoming byte (and hence for new 3£3 table), and generate the output for edge and direction.
Some implementation details are given below, where we show a 3£256 array. Other memory configurations are also possible.

1. Read data from input (i pixel) when new data is available (i.e. if i valid = ’1’)

2. Write the new data into the appropriate location as shown below. The first byte of input data (after reset) shall be written into row 1 column 1. The next input data shall be written into row 1 column 2, and so on. Proceed to the first column of the next row when the present row of memory is full.
256 bytes
a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ::: a255 a256
3 rows b1 xx xx xx xx xx xx xx xx xx xx xx xx … xx xx
xx xx xx xx xx xx xx xx xx xx xx xx xx … xx xx

3. The following shows a snapshot of the memory when row 3 column 3 is ready.
Row Idx
1^st a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ::: a255 a256
2^nd b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 ::: b255 b256
3^rd c1 c2 c3 xx xx xx xx xx xx xx xx xx xx …. xx xx

4. At this point, perform the operations on the convolution table below:
a1 a2 a3
b1 b2 b3
c1 c2 c3
Note: This requires 2 or 3 memory reads to retrieve the values from the memory
(depending on how you design your state machine). Come up with a good design so
that the above write and read can be done in parallel.
5. When the next pixel (c4) arrives, you will perform the operation on the next 3£3 convolution table:
a2 a3 a4
b2 b3 b4
c2 c3 c4

6. When row 3 is full, the next available data shall be overwritten into row 1 column 1. Although physically this is row 1 column 1, virtually it is row 4 column 1. Note that the operations will not proceed until the 3rd element of 4th row (d3) is available in which case the operation will be performed on the following table based on the virtual row index as depicted in the following figure.
Virtual
Row Idx
4th d1 d2 d3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 ::: a255 a256
2nd b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 ::: b255 b256
3rd c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 ::: c255 c256
the convolution table:
b1 b2 b3
c1 c2 c3
d1 d2 d3

7. Moving the 3£3 table over the 256£256 memory and performing the operation is in fact a convolution process. Regarding that the operations will start at the 3rd row of 256£256 memory and at the 3rd element of each row, the number of 3£3 tables on which the operations will be performed, is calculated by: 254£ 254 = 64516.
Your memory arrays shall be formed using instances of the 1£256 entry memory (provided in Ram.vhd), where each entry is 8 bits wide.

Note: The inputs to the memory are registered and the outputs from the memory are unregistered.
The figures below show the behaviour of memory for a write operation, a read
operation, and a write followed by two reads.

SPECIFICATION

The Sobel edge detection system detects edges in images using the Sobel operator. The image pixels will be supplied in raster scan order (i.e. rows are scanned left to right and top to bottom.) The edge detector will serially output data which contains edge information. The system should be synchronized by a system clock. The system should be designed in such a way that images of various size can be processed.

OBJECTIVES

The objective of our Sobel edge detection system is to perform the process of edge
detection, including storing a portion of the input image, filtering, comparing and determining the edge pixels.
Frequently, the gray level of a pixel is assigned a value in the range 0 to 255, with 0 corresponding to black, 255 corresponding to white, and shades of gray distributed over the middle values [6]. This value can be represented by an 8-bit vector. Since the filter outputs are calculated by Equations (2), (3), (5) and (6), we need 2 more bits to represent the partial summation magnitude, and one more bit to represent the sign bit of the subtraction. As a result, we need 11 bits to represent the filtering output. In order to use a standard bus, 12-bit vectors are used to represent the four filtering outputs. After edge detection, each edge pixel is assigned to the foreground value (255), while non-edge pixels are assigned to the background value (0). In the previous example, M is equal to 68. If the THRESHOLD is less than 68, then the center pixel in the window is declared to be part of an edge and its value is set to be the foreground value (255). Otherwise, the center pixel is not declared to be an edge pixel and the background value (0) is assigned to it.

SYSTEM LEVEL DECOMPOSITION OF SOBEL EDGE DETECTOR

BLOCK DIAGRAM

Block diagram of the Sobel edge detection system

Decomposition of the Sobel edge detection system

FUTURE SCOPE

1. Develop an interface for automatically capturing and changing the generics

In this project, we explained the generics and their usage. We discussed that there are two
places in the VHDL codes where the actual values of the generics are given the architecture body or the configuration body. Defining the generics in the configuration body allows design reuse. It is a better solution.
The VHDL models can be developed automatically by the SGE tool. When developing a design entity using the SGE tool, the generics can be declared and assigned value by using SGE Symbol Attribute tool.

2. A hardware architecture of the Sobel algorithm for edge detection is proposed in this paper. The technology of realizing the edge detector for obtaining the movement parameters of lateral vehicle in VCAS by FPGA provides a real time technique, which replaces programming on the microprocessor and releases the computation load of microprocessor. This approach is efficient and reliable, can be easily realized via SoC or ASIC as a special structure of the economical embedded system instead of high performance microprocessor.

CONCLUSION

We have verify and synthesise the module of image processing using VHDL and also verify and synthesise the function of Horizontal Filter, Vertical Filter, Diagonal Left Filter And Diagonal Right Filter.

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